7 points | by ihsw 14 hours ago
1 comments
ScholarlyArticle: "Vistara: Making CXL Real—Full Path from ASIC Design and OS Support to Hyperscale Deployment" (2026) https://aisystemcodesign.github.io/papers/isca26/vistara_cam...
TIL there are 2x 2.5GbE PCI-E HAT adapters for Pi 5.
How to attach RAM to the new NVLink/UALink fiber buses?
ScholarlyArticle: "Vistara: Making CXL Real—Full Path from ASIC Design and OS Support to Hyperscale Deployment" (2026) https://aisystemcodesign.github.io/papers/isca26/vistara_cam...
TIL there are 2x 2.5GbE PCI-E HAT adapters for Pi 5.
How to attach RAM to the new NVLink/UALink fiber buses?