They've shown the calculation for number of concurrent requests limited by kv cache size. I guess for each new request loaded into the queue, the kv cache for that context will need to be loaded from a supporting storage server, that will need to have a lot of ram to store the active caches of multiple requests?
Ah, this prompted a few questions from me. Perhaps someone with more hardware background could chime in.
They don't really show it here, but supposedly a Cerebras' chip is sub-divided into a 2D mesh of what they call PEs (cores). So data flow generally flows in two axis, and maintains consistent timings to its 4 neighboring cores. They show the layers flowing from left-to-right being streamed by PEs, but I wonder how true that ends up being: maybe the communications are easier to stream via diagonals, or some other shape that has better topology for data flow.
Then, even from die shots of CPUs and GPUs we often see that cores are tiled as squares, and those don't have the same cross-core connection and streaming requirement. Now, I assume that some parts of what we call a core can be moved around more freely while maintaining whatever power/heating/timing requirements we have, so perhaps it's easier to 'force' a square by moving those loose parts around. But why do we confine those to squares? Is super-core layout just something not worth investing time into, like how interconnects are timed, non-convex tilings, and distances to I/O?
And for streaming architectures like Cerebras, why aren't other types of tilings considered, something like a hexagon grid? This could have 3 inputs / 3 outputs, which could allow more complex data flow (?). Similarly, we could have 8 connections with longer diagonals in a square tiling, etc.
I guess, what are the tradeoffs in place such that so many chip designs seem to reuse square tilings both locally and globally?
The reason 2D grids work well is because you can split tensor axes along whatever dim you want across PEs (batch, sequence, hidden, etc.). And your per PE code is relatively simple. It's of the type : get data from neighbor, compute my subtensor, send to neighbor. And you can implement broadcasts and reductions along any axis.
The EDA tools that are used to design chips do not support diagonal wires so that kind of rules out hexagonal grids. With only horizontal and vertical wires you end up with rectangular/square grids or rings.
If that is so, would it be entirely to decrease search space for layout algorithms? I believe there isn't anything in the fabrication process that couldn't model diagonals.
I could see that square packing is more simple, but by shifting elements per row I don't see why it couldn't propagate at odd angles.
> The total number of concurrent requests represents the number of simultaneous requests moving through the pipeline at any point in time. Unlike a GPU batch, those requests don’t wait for one another to finish, they stream through the pipeline continuously.
What do they mean by “unlike a GPU batch”? It’s not a hardware limitation of GPUs right? It’s just the scaffolding to do this in software isn’t available right
It's describing a different type of parallelism - pipeline parallelism. The network is laid out spatially on the wafer in CB's case. So weights are stationary and activations flow. A GPU is going to process the network one layer at a time. GPUs also use other types of parallelism (tensor and expert mainly in inference). Pipeline parallelism doesn't make much sense on a GPU for inference.
I think the point is they need several wafers to fit the model. Data parallelism between requires too much bandwidth (they only have so much edge real estate for io) so you have to do pipeline parallelism with say one layer per wafer. No one does it on gpu unless you can’t fit the model in one fast network domain (which is 72 GPUs nowadays for Nvidia). There is a Dwarkesh episode from like two months ago that explains this reasonably accurately.
From reading xpct's comment in this thread it seems like they use effectively a very deep and wide pipeline by tiling the cores without central clocking or dispatch. In theory if a GPU is centrally organized it could simulate this behaviour, but I imagine that creates transfer overhead. Just speculating though.
A wafer looks pretty big. I'm surprised it has only 44GB of memory available. Doesn't that seem a tad .... low? I'm not a hardware person, but I would have assumed much more memory would fit into a wafer?
Extreme speeds are actually interesting if you think about it. We are apparently getting some interesting results from LLMs nowadays. If they would put 100x effort in 10% the time it takes, or imagine 1% where how long tool calls take become the bottleneck, that would actually probably feel like a really special kind of "super intelligence".
I think that just like there's tons of different kind of "superheroes" and nobody disputes whether they're genuinely deserving of the name or not, there could be many valid types of super intelligence.
If something is roughly as intelligent as a normal human expert in a given area, but 100 times faster, that would be a valid example of super intelligence.
I'm sure that by some definitions like this we've already discovered narrow super intelligence.
For example - breadth of knowledge. Is knowledge a kind of intelligence? If so then current agents absolutely have a breadth of knowledge which is superhuman.
This is why I think there will be selective pressure for fast tools. It’s like an evolutionary process and fast tools will be preferred and created. It’s already happening and also why I think computer use is a dead end.
At 20 kW average consumption per WSE-3T wafer this gives roughly 1.18 MW for the whole system. Assuming 1500 tokens per second and 190 concurrent requests this gives 4.1 J/token. Which is good I suppose for the size of the model?
For a fairly weak comparison, modern Bitcoin mining chips are around 13J/TH, so around 0.32TH per token, or 320 billion double-sha256 mining operations per token served by this system. Peanuts are also about 4200 Joules, or almost exactly 1000 tokens per nut assuming you could efficiently turn it into electricity to run this chip. Just as a frame of reference, I don't think this actually serves to make any point.
could push kv-cache to off chip cheaper storage like dram. Inference engine manages decode for a single user to run to completion before decode a different users so kv-cache fetch from dram to sram is limited.
I'd want to know is what a 59-wafer pipeline costs in failure domain. The GPU deployment can lose a node and degrade; Because, here the model is the rack, so one bad wafer takes the whole thing down, and a pipeline that has to be live end to end doesn't get a rolling upgrade. How do you drain one?
They've shown the calculation for number of concurrent requests limited by kv cache size. I guess for each new request loaded into the queue, the kv cache for that context will need to be loaded from a supporting storage server, that will need to have a lot of ram to store the active caches of multiple requests?
Cerebras is good on paper but all I can reasonably access is "GPT OSS 120b, Qwen 3.8 27B" which aren't very good for my use.
Openrouter on nitro gets me there. Although the TPS is 5X less still.
I have tried GPT OSS 120b on cerebras and it flies. But it's mostly wrong.
Ah, this prompted a few questions from me. Perhaps someone with more hardware background could chime in.
They don't really show it here, but supposedly a Cerebras' chip is sub-divided into a 2D mesh of what they call PEs (cores). So data flow generally flows in two axis, and maintains consistent timings to its 4 neighboring cores. They show the layers flowing from left-to-right being streamed by PEs, but I wonder how true that ends up being: maybe the communications are easier to stream via diagonals, or some other shape that has better topology for data flow.
Then, even from die shots of CPUs and GPUs we often see that cores are tiled as squares, and those don't have the same cross-core connection and streaming requirement. Now, I assume that some parts of what we call a core can be moved around more freely while maintaining whatever power/heating/timing requirements we have, so perhaps it's easier to 'force' a square by moving those loose parts around. But why do we confine those to squares? Is super-core layout just something not worth investing time into, like how interconnects are timed, non-convex tilings, and distances to I/O?
And for streaming architectures like Cerebras, why aren't other types of tilings considered, something like a hexagon grid? This could have 3 inputs / 3 outputs, which could allow more complex data flow (?). Similarly, we could have 8 connections with longer diagonals in a square tiling, etc.
I guess, what are the tradeoffs in place such that so many chip designs seem to reuse square tilings both locally and globally?
A few years old now, but their co-founder whiteboards how their chips work https://www.youtube.com/watch?v=7GV_OdqzmIU
The reason 2D grids work well is because you can split tensor axes along whatever dim you want across PEs (batch, sequence, hidden, etc.). And your per PE code is relatively simple. It's of the type : get data from neighbor, compute my subtensor, send to neighbor. And you can implement broadcasts and reductions along any axis.
The EDA tools that are used to design chips do not support diagonal wires so that kind of rules out hexagonal grids. With only horizontal and vertical wires you end up with rectangular/square grids or rings.
If that is so, would it be entirely to decrease search space for layout algorithms? I believe there isn't anything in the fabrication process that couldn't model diagonals.
I could see that square packing is more simple, but by shifting elements per row I don't see why it couldn't propagate at odd angles.
> The total number of concurrent requests represents the number of simultaneous requests moving through the pipeline at any point in time. Unlike a GPU batch, those requests don’t wait for one another to finish, they stream through the pipeline continuously.
What do they mean by “unlike a GPU batch”? It’s not a hardware limitation of GPUs right? It’s just the scaffolding to do this in software isn’t available right
It's describing a different type of parallelism - pipeline parallelism. The network is laid out spatially on the wafer in CB's case. So weights are stationary and activations flow. A GPU is going to process the network one layer at a time. GPUs also use other types of parallelism (tensor and expert mainly in inference). Pipeline parallelism doesn't make much sense on a GPU for inference.
I think the point is they need several wafers to fit the model. Data parallelism between requires too much bandwidth (they only have so much edge real estate for io) so you have to do pipeline parallelism with say one layer per wafer. No one does it on gpu unless you can’t fit the model in one fast network domain (which is 72 GPUs nowadays for Nvidia). There is a Dwarkesh episode from like two months ago that explains this reasonably accurately.
From reading xpct's comment in this thread it seems like they use effectively a very deep and wide pipeline by tiling the cores without central clocking or dispatch. In theory if a GPU is centrally organized it could simulate this behaviour, but I imagine that creates transfer overhead. Just speculating though.
A wafer looks pretty big. I'm surprised it has only 44GB of memory available. Doesn't that seem a tad .... low? I'm not a hardware person, but I would have assumed much more memory would fit into a wafer?
It's SRAM. It's the equivalent of 44 GB of CPU cache.
Exactly, which is why it’s so incredibly fast. And expensive.
traditional SRAM memory has 6 transistors per bit. Dense SRAM can have two transistors.
Wafers can have trillions of transistors, 10-16 times more than the 4 trillion of the WSE-3.
1 Terabyte of SRAM per wafer will be the upper limit for a few years [1].
[1] https://youtu.be/vbqKClBwFwI?si=gbBeZ1B66_eGI81Z
SRAM doesn't shrink as well as other types of circuitry do when process nodes advance.
Ok I'm sold, where to buy? :D
If you made the mistake of buying their stock the past few weeks, you might wish you hadn't (or maybe it's an opportunity to buy low yada yada)
Extreme speeds are actually interesting if you think about it. We are apparently getting some interesting results from LLMs nowadays. If they would put 100x effort in 10% the time it takes, or imagine 1% where how long tool calls take become the bottleneck, that would actually probably feel like a really special kind of "super intelligence".
It would absolutely be a phase change in practical utility, but it still wouldn't be "super intelligence".
I think that just like there's tons of different kind of "superheroes" and nobody disputes whether they're genuinely deserving of the name or not, there could be many valid types of super intelligence.
If something is roughly as intelligent as a normal human expert in a given area, but 100 times faster, that would be a valid example of super intelligence.
I'm sure that by some definitions like this we've already discovered narrow super intelligence.
For example - breadth of knowledge. Is knowledge a kind of intelligence? If so then current agents absolutely have a breadth of knowledge which is superhuman.
This is why I think there will be selective pressure for fast tools. It’s like an evolutionary process and fast tools will be preferred and created. It’s already happening and also why I think computer use is a dead end.
At 20 kW average consumption per WSE-3T wafer this gives roughly 1.18 MW for the whole system. Assuming 1500 tokens per second and 190 concurrent requests this gives 4.1 J/token. Which is good I suppose for the size of the model?
For a fairly weak comparison, modern Bitcoin mining chips are around 13J/TH, so around 0.32TH per token, or 320 billion double-sha256 mining operations per token served by this system. Peanuts are also about 4200 Joules, or almost exactly 1000 tokens per nut assuming you could efficiently turn it into electricity to run this chip. Just as a frame of reference, I don't think this actually serves to make any point.
Each Nvidia rack is 120 kilowatts, so the power consumption is about the same as 10 racks of GPUs, FWIW.
Cerebras is the Transmeta of the AI wave.
could push kv-cache to off chip cheaper storage like dram. Inference engine manages decode for a single user to run to completion before decode a different users so kv-cache fetch from dram to sram is limited.
I'd want to know is what a 59-wafer pipeline costs in failure domain. The GPU deployment can lose a node and degrade; Because, here the model is the rack, so one bad wafer takes the whole thing down, and a pipeline that has to be live end to end doesn't get a rolling upgrade. How do you drain one?